1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the contact level of a semiconductor device, in which contact areas, such as gate electrodes and drain and source regions, are connected to the metallization system of the semiconductor device on the basis of electrochemical deposition techniques.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very high number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. However, the continuing scaling of feature sizes involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, a large number of field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain terminal and a source terminal.
On the basis of the field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, memory devices and the like. Due to the reduced dimensions, the operating speed of the circuit components has been increased with every new device generation, wherein, however, the limiting factor of the finally achieved operating speed of complex integrated circuits is no longer the individual transistor element but the electrical performance of the complex wiring fabric, which may be formed above the device level including the actual semiconductor-based circuit elements, such as transistors and the like. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level, on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as vias. These interconnect structures comprise an appropriate metal and provide the electrical connection of the individual circuit elements and of the various stacked metallization layers.
Furthermore, to establish a connection of the circuit elements with the metallization layers, an appropriate vertical contact structure is provided, which connects to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and to a respective metal line in the metallization layer. The contact structure may comprise contact elements or contact plugs formed in an interlayer dielectric material that encloses and passivates the circuit elements. Upon shrinkage of the critical dimensions of the circuit elements in the device level, the dimensions of metal lines, vias and contact elements also have to be adapted to the reduced dimensions, thereby requiring sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower-lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required “packing density” in accordance with density of circuit elements in the device level.
Upon further reducing the dimensions of the circuit elements, for instance using critical dimensions of 50 nm and less, the contact elements in the contact level may have to be provided with appropriate critical dimensions on the same order of magnitude. The contact elements may typically represent plugs, trenches and the like which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically, the interlayer dielectric material may be formed first and may be patterned to receive contact openings, which may extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. For this purpose, openings of very different depth may have to be formed in the interlayer dielectric material in order to connect to gate electrode structures or any other conductive lines formed above the semiconductor layer, while other contact openings have to be extended down to a semiconductor layer, i.e., any contact areas formed therein. In particular, in densely packed device regions, the lateral size of the drain and source areas and thus the available area for the contact regions may be 100 nm and less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy, while the difference in etch depth may additionally contribute to the overall complexity of the patterning process. After exposing the contact areas, frequently provided in the form of metal silicide regions, a barrier material has to be provided, for instance in the form of a material system including titanium and titanium nitride, wherein the titanium material may provide the required adhesion characteristics, while the titanium nitride material may preserve integrity of the interlayer dielectric material during the subsequent deposition of the tungsten material, which may be accomplished on the basis of sophisticated chemical vapor deposition (CVD) techniques in which a direct contact between silicon dioxide-based materials and the deposition ambient for depositing the tungsten material is to be avoided. Typically, the actual deposition of the tungsten material may be preceded by the deposition of a nucleation layer based on tungsten, which may be accomplished by a dedicated deposition step, after which the actual fill material may be provided. After the deposition of these materials, any excess material may be removed, for instance, by chemical mechanical polishing (CMP), thereby forming the insulated contact elements in the interlayer dielectric material. Although the process sequence for patterning the contact openings and filling these openings with barrier materials and tungsten results in contact elements having a desired contact resistivity for semiconductor devices with critical dimensions of 50 nm, a further reduction of the size of the transistors may result in an increased contact resistivity, which may no longer be compatible with the device requirements. That is, upon further device scaling, the increased contact resistivity, which may result from conventional tungsten-based contact regimes, may represent a limiting factor of the operating speed of the integrated circuits, thereby at least partially offsetting many advantages obtained by the further reduction of the critical dimensions in the device level.
One of the reasons for the inferior contact resistivity in tungsten-based contact technologies is the requirement for barrier materials, possibly in combination with a nucleation layer, which may have an increased resistivity compared to the subsequent tungsten fill material. Since a thickness of the barrier materials and the nucleation layer may not be arbitrarily reduced without jeopardizing the effect of this material system, the amount of less conductive materials relative to the tungsten material may thus increase, thereby over-proportionally contributing to an increased contact resistance. For these reasons, it has been suggested to use other materials or deposition regimes in which the presence of a barrier material of reduced conductivity may be avoided. For example, it has been proposed to use wet chemical deposition techniques, such as the electrochemical deposition in the form of an electroless plating process, in order to fill in an appropriate metal material, thereby obtaining a superior fill behavior in order to avoid the creation of any voids or other deposition-related irregularities, which may frequently be observed in complex CVD-based techniques in which a complex material system may have to be deposited within sophisticated contact openings, in particular when these openings may have very different depths. Although the electroless deposition technique may be very advantageous with respect to the gap-filling capability and the selection of an appropriate contact material, thereby providing the possibility of avoiding any barrier materials, it turns out that, in particular, the different fill heights of the contact openings above gate electrode structures and drain and source regions may contribute to a disadvantageous surface topography after the fill process, which may negatively affect the further processing of the device, as will be described in more detail with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 and a semiconductor layer 102, such as a silicon-based semiconductor material and the like. The semiconductor layer 102 and the substrate 101 may represent a silicon-on-insulator (SOI) configuration or a bulk configuration in which the semiconductor layer 102 represents a portion of a crystalline semiconductor material of the substrate 101. The semiconductor layer 102 comprises a plurality of semiconductor regions 102A, 102B in combination with isolation structures 102C, such as a shallow trench isolation and the like. It should be appreciated that the semiconductor regions 102A, 102B may also be laterally separated by an isolation structure, depending on the required overall circuit configuration. In the example shown, the semiconductor regions 102A, 102B may represent a substantially continuous semiconductor material in which a plurality of drain and source regions 161 are provided for transistors 160C, 160B. For example, the transistors 160C, 160B may represent closely packed transistor elements of the same conductivity type as may frequently be required in certain device regions, such as RAM areas of a complex logic circuit and the like. The transistors 160B, 160C comprise gate electrode structures 150B, 150C, respectively, which may have the same configuration and which may have substantially the same structure as a conductive line 150A, which may also represent a gate electrode structure when extending to a further semiconductor region, or which may represent an electrical connection so as to electrically connect the semiconductor region 102A or the drain and source region 161 of the transistor 160C with another active region of the semiconductor layer 102. In the following, the conductive line 150A may also be referred to as a gate electrode structure having the same configuration as the gate electrode structures 150B, 150C. When appropriate, the gate electrode structures 150A, 150B, 150C may commonly be referred to as gate electrode structures 150. As illustrated, the gate electrode structures 150 comprise a gate insulation layer 152 that separates an electrode material 151 from the under-lying semiconductor regions 102A, 102B. Furthermore, a metal-containing material 154 is usually provided in the gate electrode structures 150 in order to enhance the overall series conductivity and also reduce contact resistivity of the gate electrode structures 150. In the example shown, the metal-containing regions 154 may be comprised of a metal silicide, such as nickel silicide, nickel/platinum silicide and the like. In this case, the electrode material 151 may comprise a significant portion of silicon material. Furthermore, the gate electrode structures 150 may comprise a spacer structure 153 having any appropriate lateral dimension as required for appropriately defining the dopant profile of the drain and source regions 161 and of metal silicide regions 162, which are usually provided in the drain and source regions 161 in order to reduce the contact resistivity. In the example shown, an additional semiconductor material 102E is provided between the gate electrode structures 150A, 150C, which may thus locally increase the height of the semiconductor layer 102 between the structures 150A, 150C. A corresponding configuration may be advantageous in some cases when a contact is to be established between the gate electrode structure 150A and a drain or source region of the transistor 160C, as will be described later on in more detail. In this case, a metal silicide 163 may be formed in the additional semiconductor region 102E.
Furthermore, an interlayer dielectric material 120 is formed so as to enclose and passivate the gate electrode structures 150 and thus the transistors 160B, 160C, wherein any appropriate composition of materials and material layers may be applied. For example, a silicon nitride-based material 121 may be formed on the gate electrode structures 150, followed by a silicon dioxide-based material and the like. Furthermore, a first contact element 123 is formed in the interlayer dielectric material 120 and extends to a metal-containing region 154, which may also be considered as a contact area of the gate electrode structure 150A. In the example shown, the gate electrode structure 150A may also act as a “local interconnect structure” wherein the gate electrode material 151 may be connected to the semiconductor region 102E and thus to a drain or source region of the transistor 160C. For this purpose, the contact element 123 has appropriate lateral dimensions and a position in order to contact the metal silicide region 163. On the other hand, a second contact element 124 extends to a drain or source region of the transistor 160C, 160B, i.e., to the metal silicide region 162, wherein the lateral dimension of the contact element 124 is appropriately adapted to the overall device geometry, as previously discussed. That is, in sophisticated applications, at least one lateral dimension of the contact element 124, i.e., the horizontal extension in FIG. 1, may be approximately 50 nm and less. The contact elements 123, 124 are comprised of any appropriate material, which may be provided on the basis of electroless plating techniques in order to obtain a desired fill behavior. Furthermore, in some approaches, the contact elements 123, 124 are formed of a metal that may be directly deposited on the regions 154, 163 and 162 in order to provide a highly efficient process flow and to reduce the presence of any barrier materials, which typically have a reduced conductivity compared to the actual contact metal, as discussed above.
The semiconductor device 100 as illustrated in FIG. 1 may be formed on the basis of the following conventional process techniques. After forming the isolation structure 102C and defining the basic conductivity type of the semiconductor regions 102A, 102B, the gate electrode structures 150 are formed by depositing or otherwise forming appropriate materials for the gate insulation layers 152 and depositing one or more electrode materials, such as polysilicon and the like, in combination with other materials that may be required for patterning the resulting layer stack. By means of sophisticated lithography and etch techniques, the electrode material or materials 151 and the gate dielectric material 152 is patterned in accordance with the design rules of the device 100. Thereafter, the drain and source regions 161 may be formed on the basis of the sidewall spacer structure 153, wherein, if required, additional process steps may be performed in order to implement performance increasing mechanisms, such as strain-inducing semiconductor alloys and the like.
If required, the additional semiconductor material 102E may be provided, for instance, by masking the gate electrode structures 150 and exposing a portion between the structures 150A, 150C by means of appropriate lithography and etch techniques. Thereafter, the material 102E may be formed on the basis of selective epitaxial growth techniques, for instance in the form of a silicon/germanium alloy, a silicon material and the like, which may have a desired in situ doping concentration in order to obtain a desired high conductivity. In other cases, the region 102E may not be necessary and the further processing may be continued by forming the metal silicide regions 154, 162 and possibly the region 163 based on conventional silicidation techniques.
Next, the interlayer dielectric material 120 is deposited, for instance by plasma enhanced CVD techniques, thermally activated CVD processes and the like. In the example shown, the layer 121 is deposited, for instance, as a silicon nitride material, followed by the deposition of a silicon dioxide material, which may subsequently be planarized, for instance by CMP. Thereafter, an etch mask is formed by using sophisticated lithography techniques, thereby defining the lateral size and position of contact openings to be formed in the interlayer dielectric material 120. Consequently, during this patterning process, the position of any gate contacts, such as the contact element 123, and other contacts connecting to the semiconductor layer 102, such as the contact element 124, are defined in position and lateral size. In the specific example shown in FIG. 1, the lateral size of the contact element 123 is selected so as to connect to the gate electrode structure 150A and to the semiconductor layer 102, thereby requiring an increased lateral size compared to the contact element 124. A corresponding contact regime may be highly advantageous in memory areas, thereby avoiding additional interconnect structures in the metallization level of the device 100, which is to be formed above the interlayer dielectric material 120 in a further advanced manufacturing stage. On the other hand, providing contact openings with different depth and different lateral size may additionally contribute to a further complexity of the corresponding etch process, which may result in an increased degree of variation of critical dimensions of the contact elements 123, 124. For this reason, the material 102E may be provided in order to cause less non-uniformity during the complex patterning process.
After forming the contact openings so as to expose the regions 154, 163 and 162, acting as contact areas, a contact metal may be deposited on the basis of a wet chemical deposition process such as electroless plating. During an electroless plating process, an appropriate electrolyte solution is provided which may comprise a reducing agent in combination with a salt including the desired metal component in addition to other chemical agents, thereby resulting in the deposition of metal on an appropriate surface, such as a metal-containing material acting as a catalyst material, such as the regions 154, 163 and 162, without requiring the application of an external electrical power. Thus, during the deposition process, the metal material may grow on the contact areas 154, 163, 162 on the basis of an auto catalyst reaction, i.e., contact metal on contact area, wherein, during the further process, an appropriate reducing agent may provide the deposition of contact metal on contact metal. Consequently, substantially the same growth conditions may occur and may result in a different final growth height of the contact elements 123, 124 due to the different start height level, for instance above the gate electrode structure 150A and above the drain and source regions 161. Hence, upon completely filling the contact element 124, a significant local overgrowth of the contact element 123 is caused, as illustrated in FIG. 1. Consequently, the resulting surface topography may require additional process steps for removing any excess material of the contact element 123, which may, however, contribute to contamination of the dielectric material 122, thereby increasing the probability of creating leakage paths and the like. On the other hand, underfilling the contact element 124, i.e., providing the dielectric material 122 with an increased initial thickness in order to provide superior conditions for a subsequent planarization process in order to remove excess material of the dielectric layer in combination with the excess metal of the contact element 123, may be less than desirable since patterning the increased thickness of the dielectric material 122 may result in additional patterning related non-uniformities.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.